2.5 Addressing Modes

Much of the novelty and complexity of the PDP11 instruction set lies in the variety of addressing modes which may be used for defining the source and destination operands.

The addressing modes which are used in “m40.s” are described below.

Register Mode:

The operand resides in one of the general registers, e.g.

    clr r0
    mov rl,r0
    add r4,r2

In the following modes, the designated register contains an address value which is used to locate the operand.

Register Deferred Mode:

The register contains the address of the operand, e.g.

    inc (rl)
    asr (sp)
    add (r2),rl

Autoincrement Mode:

The register contains the address of the operand. As a side effect, the register is incremented after the operation, e.g.

    clr  (rl)+
    mfpi (r0)+
    mov  (r1)+,r0
    mov  r2,(r0)+
    cmp (sp)+,(sp)+

Autodecrement Mode:

The register is decremented and then operand, e.g.

    inc -(r0)
    mov -(r1),r2
    mov (r0)+,-(sp)
    clr -(sp)

Index Mode:

The register contains a value which is added to a sixteen bit word following the instruction to form the operand address, e.g.

    clr  2(r0)
    movb 6(sp),(sp)
    movb _reloc(r0),r0
    mov  -10(r2),(rl)

Depending on your viewpoint, in this mode the register is either an index register or a base register. The latter case actually predominates in “m40.s”. The third example above is actually one of the few uses of a register as an index register. (Note that “_reloc” is an acceptable variable name.)

There are two addressing modes whose use is limited to the following two examples:

    jsr pc,(r0)+
    jmp *0f(r0)

The first example involves the use of the “autoincrement deferred” mode. (This occurs in the routine “call” on lines 0785, 0799.) The address of a routine intended for execution is to be found in the word addressed by r0, i.e. two levels of indirection are involved. The fact that r0 is incremented as a side effect is not relevant in this usage.

The second example (which occurs on lines 1055, 1066) is an instance of the “index deferred” mode. The destination of the “jump” is the content of the word whose address is labelled by “0f” plus the value of r0 (a small positive integer). This is a standard way to implement a multi-way switch.

The following two modes use the program counter as the designated register to achieve certain special effects.

Immediate Mode:

This is the pc autoincrement mode. The operand is thus extracted from the program string, i.e. it becomes an immediate operand, e.g.

    add $2,r0
    add $2,(rl)
    bic $17,r0
    mov $KISA0,r0
    mov $77406,(rl)+

Relative Mode:

This is the pc index mode. The address relative to the current program counter value is extracted from the program string and added to the pc value to form the absolute address of the operand, e.g.

    bic $340,PS
    bit $l,SSR0
    inc SSR0
    mov (sp),KISA6

It may be noted that each of the modes “index”, “index deferred”, “immediate” and “relative” extends the instruction size by one word.

The existence of the “autoincrement” and “autodecrement” modes, together with the special attributes of r6, make it conveniently possible to store many operands in a stack, or LIFO list, which grows downwards in memory. There are a number of advantages which flow from this: code string lengths are shorter and it is easier to write position independent code.