2.4 Instruction Set

The PDP11 instruction set includes double, single and zero operand instructions. Instruction length is usually one word, with some instructions being extended to two or three words with additional addressing information.

With single operand instructions, the operand is usually called the “destination”; with double operand instructions, the two operands are called the “source” and “destination”. The various modes of addressing are described later.

The following instructions have been used in the file “m40.s” i.e. the file of assembly language support routines for use with the 11/40 processor. Note that N, Z, V and C are the condition codes i.e. bits in the processor status word (“ps”), and that these are set as side effects of many instructions besides just “bit”, “cmp” and “tst” (whose stated function is to set the condition codes).

adc

Add the contents of the C bit to the destination;

add

Add the source to the destination;

ash

Shift the contents of the defined register left the number of times specified by the shift count. (A negative value implies a right shift.);

ashc

Similar to “ash” except that two registers are involved;

asl

Shift all bits one place to the left. Bit 0 becomes 0 and bit 15 is loaded into C;

asr

Shift all bits one place to the right. Bit 15 is replicated and bit 0 is loaded into C;

beq

Branch if equal, i.e. if Z = l;

bge

Branch if greater than or equal to, i.e. if
N = V;

bhi

Branch if higher, i.e if C = 0 and Z = 0;

bhis

Branch if higher or the same, i.e. if C = 0;

bic

Clear each bit to zero in the destination that corresponds to a non-zero bit in the source;

bis

Perform an “inclusive or” of source and destination and store the result in the destination;

bit

Perform a logical “and” of the source and destination to set the condition codes;

ble

Branch if greater than or equal to, i.e if Z = 1 or N = V;

blo

Branch if lower (than zero), if C = l;

bne

Branch if not equal (to zero), i.e. if Z = 0;

br

Branch to a location within the range (. -128,
. +127) where “.” is the current location;

clc

Clear C;

clr

Clear destination to zero;

cmp

Compare the source and destination to set the condition codes. N is set if the source value is less than the destination value;

dec

Subtract one from the contents of the destination;

div

The 32 bit two’s complement integer stored in rn and r(n+l) (where n is even) is divided by the source operand. The quotient is left in rn, and the remainder in r(n+l);

inc

Add one to the contents of the destination;

jmp

Jump to the destination;

jsr

Jump to subroutine. Register values are shuffled as follows:

pc, rn, –(sp) = dest., pc, rn

mfpi

Push onto the current stack the value of the designated word in the “previous” address space;

mov

Copy the source value to the destination;

mtpi

Pop the current stack and store the value in the designated word in the “previous” address space;

mul

Multiply the contents of rn and the source. If n is even, the product is left in rn and r(n+l);

reset

Set the INIT line on the Unibus for 10 milliseconds. This will have the effect of reinitialising all the device controllers;

ror

Rotate all bits of the destination one place to the right. Bit 0 is loaded into C, and the previous value of C is loaded into bit 15;

rts

Return from subroutine. Reload pc from rn, and reload rn from the stack;

rtt

Return from interrupt or trap. Reload both pc and ps from the stack;

sbc

Subtract the carry bit from the destination;

sob

Subtract one from the designated register. If the result is not zero, branch back “offset” words;

sub

Subtract the source from the destination;

swab

Exchange the high and low order bytes in the destination;

tst

Set the condition codes, N and Z, according to the contents of the destination;

wait

Idle the processor and release the Unibus until a hardware interrupt occurs.

The “byte” version of the following instructions are used in the file “m40.s”, as well as the “word” versions described above: