Receiver Status Register (klrcsr)

bit 7

Receiver Done. (A character has

been transferred into the

Receiver Data Buffer Register.);

bit 6

Receiver Interrupt Enable.

(When set, an interrupt is

caused every time bit 7 is set.);

bit 1

Data terminal ready;

bit 0

Reader Enable. Write only.

(When set, bit 7 is cleared.).

Receiver Data Buffer Register (klrbuf)

bit 15

Error indication, when set.

bits 7-0

Received character, Read

only.

Transmitter Status Register (kltcsr)

bit 7

Transmitter ready. This is

cleared when data is loaded

into the Transmitter Data

Buffer, and is set when the

latter is ready to receive

another chatacter;

bit 6

Transmitter Interrupt Enable.

(when set, causes an

interrupt to be generated

whenever bit 7 is set.)

Transmitter Data Buffer Register (kltbuf)

bits 7-0

Transmitted data. Write only.