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The discussion in Section One introduced three places where the occurrence of a trap or interrupt was expected:
“main” (1564) calls “fuibyte” repeatedly until a negative value is returned. This will occur after a “bus timeout error” has been encountered with a subsequent trap to vector location 4 (line 0512);
The clock has been set running and will generate an interrupt every clock tick i.e. 16.7 or 20 milliseconds;
Process #1 is about to execute a “trap” instruction as part of the system call on “exec”.
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